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81.3 MB
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0E0067B4CB763533AD39D9CE7278A6C50B000439
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Added:
Dec. 18, 2025, 5:01 p.m.
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(Last updated: Dec. 18, 2025, 5:18 p.m.)
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| Li Y. AI-Enhanced Circuit Design and Advanced Memory Computing 2025.pdf | 81.3 MB |
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NOTE
SOURCE: Li Y. AI-Enhanced Circuit Design and Advanced Memory Computing 2025
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COVER
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MEDIAINFO
Textbook in PDF format Welcome to this collection of presentations from our comprehensive volume on AI-Enhanced Circuit Design and Advanced Memory Computing. This book presents cutting-edge research and developments from leading experts shaping the future of integrated circuit architectures and computing paradigms. Section I covers foundational principles of AI-driven circuit design, featuring how AI empowers the design and optimization of analog-to-digital converters. Section II delves into Near-Memory Computing (NMC), with an in-depth exploration of NMC architectures and their transformative potential for computing efficiency. Section III focuses on Processing-In-Memory paradigms, where ReRAM-based accelerators are tailored for scientific computing workloads, alongside a comprehensive overview of in-memory hyperdimensional computing algorithms, circuit implementations, and applications. The Chapter 1 discusses the use of Artificial Intelligence (AI) to optimize the performance and automate the design of analog and mixed-signal integrated circuits, with emphasis on Analog-to-Digital Converters (ADCs). A survey of conventional and computational-intelligence methods and EDA tools is given as a motivation to use Artificial Neural Networks (ANNs) to synthesize more efficient analogdigital interfaces. A tutorial description of main practical aspects is given, including dataset generation, ANN modeling, training and optimization of network hyperparameters. Several examples and case studies are shown to demonstrate its application at different abstraction levels. At system level, ANNs are used in combination with behavioral simulation for the optimization of ADCs based on Sigma-Delta Modulators (SDMs). At circuit level, SPICE-like simulation is combined with ANNs to automate transistor sizing and biasing of Operational Transconductance Amplifiers (OTAs). A comparison with other optimization methods – such as genetic algorithms, simulated annealing and gradient descent – is discussed, demonstrating that the AI-empowered methodologies yield to more efficient design solutions in terms of performance metrics and computational resources. As a new computing paradigm, hyperdimensional computing (HDC) has gradually manifested its advantages in edgeside intelligent applications due to its interpretability, hardware-friendliness and robustness. The core of HDC is to encode input sample into a hypervector, and then use it to query the class hypervectors. Compared with the conventional architecture that uses CMOS-based circuits to complete the computation in the query operation, the hyperdimensional associative memory (HAM) enables the query operation to be completed in memory, which significantly reduces delay and energy consumption. In our works, HDC especially in-memory HDC, has been explored in depth from both algorithm and circuit levels. At the algorithm level, the training method for HDC is proposed to narrow the accuracy gap between HDC and neural networks, so that HDC can deal with more complex applications. At the circuit level, simplified HAM architecture and circuits are proposed to further reduce area and energy consumption. The algorithm and circuits co-design makes accuracy loss negligible. Experimental results show that the proposed designs can be used in a wide range of edge-side application scenarios. This collection offers a focused yet broad perspective on emerging AI-enhanced design methodologies and memory-centric computing architectures, serving as a valuable resource for researchers, engineers, and technologists advancing next-generation computing systems
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